An ASIC Low Power Primer: Analysis, Techniques and by Rakesh Chadha

By Rakesh Chadha

This e-book presents a useful primer at the strategies used in the layout of low strength electronic semiconductor units. Readers will enjoy the hands-on technique which begins shape the ground-up, explaining with easy examples what energy is, the way it is measured and the way it affects at the layout strategy of application-specific built-in circuits (ASICs). The authors use either the Unified strength layout (UPF) and customary energy structure (CPF) to explain intimately the ability motive for an ASIC after which consultant readers via various architectural and implementation ideas that would aid meet the ability motive. From examining procedure strength intake, to suggestions that may be hired in a low strength layout, to a close description of 2 trade criteria for taking pictures the ability directives at numerous stages of the layout, this booklet is stuffed with details that might supply ASIC designers a aggressive part in low-power design.

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Extra resources for An ASIC Low Power Primer: Analysis, Techniques and Specification

Example text

The distribution of the ZN toggles into path-specific toggles uses the same ratio as the toggle rates of inputs A1 and A2. 2 Power Computation for Basic Cells and Macros 51 For A1->ZN toggle rate, we use A1->ZN internal power table and for A2->ZN toggle rate, we use A2->ZN internal power table. As described in Chap. 2, the internal power tables can be a nonlinear table defined in terms of input slew and output capacitance. However, for simplifying the explanation, the power values for this example are depicted as scalar values independent of input slew or the output capacitance.

What is the total active (or dynamic) power dissipated in the output buffer for the VDD_IO supply? 3 Power Dissipation in IO Buffers 37 Fig. 4 mW of active power is dissipated within this output buffer from the VDD_IO supply. Because of larger output voltage and higher output loading, the active power of the output buffer is dominated by the output charging power. 2 Input IO Buffers For the input IO buffer, the overall breakdown of power is the same as for output IO buffers. One difference is that the output charging now refers to the core side pin of the IO and thus the output charging contribution is similar to that of the other core logic signals.

Internal Power For the internal power due to switching activity on ZN, the appropriate pathdependent internal power table has to be used. 7 million transitions per second toggle rate at ZN is mapped to path-specific (A1->ZN) or (A2->ZN) based upon the toggle rates of A1 and A2. The distribution of the ZN toggles into path-specific toggles uses the same ratio as the toggle rates of inputs A1 and A2. 2 Power Computation for Basic Cells and Macros 51 For A1->ZN toggle rate, we use A1->ZN internal power table and for A2->ZN toggle rate, we use A2->ZN internal power table.

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