3D Nanoelectronic Computer Architecture and Implementation by D. Crawley, K. Nikolic, M. Forshaw

By D. Crawley, K. Nikolic, M. Forshaw

It's changing into more and more transparent that the two-dimensional structure of units on computing device chips is beginning to prevent the advance of high-performance computers. 3-dimensional buildings should be had to give you the functionality required to enforce computationally extensive projects. three-D Nanoelectronic computing device structure and Implementation experiences the state-of-the-art in nanoelectronic equipment layout and fabrication and discusses the architectural features of 3-D designs, together with the potential use of molecular wiring and carbon nanotube interconnections. it is a worthwhile reference for these serious about the layout and improvement of nanoelectronic units and know-how.

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However, if direct connections were available from each PE in one layer to the corresponding PE in the next layer, then the data rate per connection would be very low—perhaps only a few kbits s−1 . The total data transfer rate would remain the same but the accompanying heat dissipation would drop dramatically, to perhaps tens of milliwatts per layer. For the final layers, if they were to contain only one or a few large-scale processing engines, then edge connections might be a realistic option.

17th Conf. on Adv. Res. 1 Introduction Research into three-dimensional (3D) electronics has continued for more than three decades and a very large number of techniques have been studied. But, until recently, there has been relatively little commercial exploitation for volume applications. Most of the motivation has previously come from a desire to reduce the physical size of systems, for example for aerospace applications, hearing aids or products such as Flash memory and mobile phones. It is also interesting to note that more work is being directed towards the development of CAD tools for the design of integrated circuits intended to be part of a 3D system.

Compared to other work, the layers used in this stack were quite thick—200 µm for the silicon and 300 µm for the diamond. Using this technique, the authors claim that a power dissipation of between 80 and 100 W could be achieved with a cubic volume of about 16 cm3 (at a peak temperature of around 73 ◦C). This would imply a stack of about 50 layers of active devices. It should be noted that, in this work, the connections between layers were made on one face of the cube. 8. Structures studied by Yamaji et al [19] An alternative possibility might be to use active device layers of isotopically enriched or purified silicon.

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